800G and 1.6T optical interconnect / silicon photonics / co-packaged optics technology and investment research

Technical bottleneck

• Bottleneck type: Capacity / qualification / packaging / testability
• Technical constraint: CPO and silicon photonics now hinge on design-for-test, fault detection, thermal co-design, and manufacturability rather than just raw device speed.
• Economic constraint: Hyperscaler qualification cycles and allocation discipline; new architectures need serviceability and standardization before broad deployment.

Adoption

• Driver: AI datacenter growth, 800G ramp, 1.6T transition, and packaging integration.
• Blocker: CPO timing shifts, thermal management, serviceability, and inventory/oversupply risk.

Product categories

800G/1.6T pluggable modules, silicon photonics PICs, lasers, co-packaged optics

Public companies exposed

COHR, LITE, CRDO, ANET, AVGO, MRVL, AAOI, AXTI

Validation signals

Coherent Q3 FY2026 revenue $1.81B +20.5% YoY and GAAP gross margin 37.7%; arXiv shows CPO still early but deployable; DFT work shows manufacturing/test issues are now first-order constraints.

Invalidation signals

If copper/AEC extends further or standardization/serviceability stalls CPO adoption.

Related product map rows

• LITE — Emerging: AI compute growth → 800G/1.6T optical interconnect demand → InP laser bottleneck → LITE dominant EML/laser supplier sold out through 2027; CPO delay extends pluggable runway · confidence low
• COHR — Emerging: 800G silicon photonics on full allocation; COHR EML lasers = critical component; CPO timing risk flagged (Semi Analysis Computex feedback) but thesis intact short-term · confidence low
• AXTI — Emerging: DIGITAL INFRA: InP substrate bottleneck for 400G/800G silicon photonics and defense/quantum applications; $632M capacity expansion confirms real demand; substrate for LiDAR/sensing also · confidence low
• ANET — Emerging: AI compute -> DC buildout -> networking bottleneck (800G/1.6T) · confidence low
• MRVL — Consensus: AI compute -> custom ASIC/silicon -> DC networking bottleneck · confidence low
• AVGO — Consensus: AI compute -> networking silicon bottleneck · confidence low
• AAOI — Early: AI compute -> DC buildout -> 800G/1.6T optics bottleneck · confidence low
• CRDO — Emerging: GPU scale-out → 800G/1.6T connectivity bottleneck (AEC active electrical cables) · confidence low
• CRDO — HiWire AEC Active Electrical Cables + optical DSP ICs: Signal retiming at 112/224 Gbps per lane in copper cables; DSP for coherent optical ZR/ZR+ · confidence high