High-bandwidth memory (HBM) — HBM3E and HBM4 technology and investment research

Technical bottleneck

• Bottleneck type: Capacity / 3D stacking yield
• Technical constraint: TSV formation through 8-12 DRAM die layers with <5 μm diameter and >50:1 aspect ratio; microbump interconnect at 40-55 μm pitch requiring <2 μm alignment; thermal management of >16 GB stacks consuming 5-7W per stack — heat must travel through silicon interposer to substrate
• Economic constraint: SK Hynix dominates HBM3E (>90% share); Samsung and Micron are ramping but 6-12 months behind; HBM wafer consumption is 2-3× DRAM wafer equivalent per GB; HBM capacity is committed years in advance to NVIDIA and AMD — effectively pre-sold supply

Adoption

• Driver: NVIDIA B200/B100 (8 stacks of 8-Hi HBM3E per GPU, 192-288 GB); AMD MI300X (8 stacks of 8-Hi HBM3); custom ASICs (AWS Trainium, Google TPU) also adopting HBM; HBM4 with 2048-bit interface for 2026-2027
• Blocker: Hynix HBM capacity expansion timeline (fabs take 2-3 years); Samsung HBM3E qualification delays; advanced packaging (CoWoS) co-bottleneck — HBM supply without CoWoS capacity does not deliver complete systems; HBM4 transition might reset qualification cycles

Public companies exposed

MU (Micron — HBM3E ramping

HBM4 in development)

NVDA (NVIDIA — primary consumer

drives allocation)

AMD (MI300X — second-largest consumer)

AVGO (Broadcom — custom ASIC HBM integration)

QCOM (Qualcomm — AI PC with HBM?)

Validation signals

MU HBM revenue guidance and capacity commitments; SK Hynix/Hynix HBM3E capacity expansion announcements; HBM lead times extending past 52 weeks; HBM pricing (premium over commodity DRAM) widening

Invalidation signals

HBM supply catching up to GPU demand (lead times normalizing); Samsung gaining >20% HBM3E share from Hynix; alternative memory technologies (GDDR7, LPDDR6 on interposer) offering near-HBM bandwidth at lower cost