AI server 48V power delivery (multiphase VRM for GPU) technology and investment research

Technical bottleneck

• Bottleneck type: Efficiency / Density / Thermal / Phase current scaling
• Technical constraint: At 0.7V output and 3,500A load, I²R losses in PCB traces, connector pins, and inductor DCR must be <2% total to stay within thermal budget. A 100-phase VRM at 2 MHz switching frequency requires careful phase-interleaving to avoid beat frequencies and EMI. Transient response: when the GPU jumps from idle (50A) to full load (3,500A) in <1 µs, the VRM must respond without voltage droop exceeding ±3% (21 mV at 0.7V) — or the GPU crashes.
• Economic constraint: MPWR's proprietary BCD (Bipolar-CMOS-DMOS) process integrates high-voltage DMOS power devices with precision CMOS control on one die. Competing with discrete solutions on efficiency, density, and cost requires process-level integration taking years to develop.

Adoption

• Driver: GPU power scaling (700W H100 → 1,500W Rubin → 2,500W Rubin Ultra); 48V bus adoption reducing I²R losses 16× vs 12V; phase count and VRM content per GPU growing 4x
• Blocker: 800V DC rack architecture may bypass 48V intermediate bus; GaN power stages could reduce phase count; Chinese DrMOS competitors (JWIT) gaining share

Public companies exposed

MPWR (Monolithic Power — multiphase controllers, DrMOS, 48V DC-DC converters), VICR (Vicor — power modules, factorized power architecture), ON (onsemi — DrMOS, smart power stages), Infineon (DrMOS, power stages), Renesas (multiphase controllers)

Validation signals

• MPWR data center revenue growing rapidly; proprietary BCD process moat
• VICR 48V/800V power modules designed into AI server reference architectures
• Phase count 4x from H100 to Rubin Ultra (analyst GPU teardowns)
• Chinese DrMOS competitor JWIT accelerating but MPWR/VICR still dominant in high-end